Free Download Advanced Silicon Test & DFT Methodologies
Published 3/2026
Created by Davide Negri
MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz, 2 Ch
Level: Expert | Genre: eLearning | Language: English | Duration: 35 Lectures ( 4h 38m ) | Size: 4.1 GB
Master scan architectures, JTAG, fault models, compression, OCC, MBIST and full tapeout DFT sign-off with Tessent & tmax
What you'll learn
✓ Master fault models, scan architectures, JTAG, test compression, at-speed testing, MBIST, and STIL protocol files.
✓ Implement scan chains, lock-up latches, OCC, and DRC rules using Siemens Tessent and Synopsys TetraMAX.
✓ Analyze ATPG reports: Fault Coverage, Test Coverage, ATPG Effectiveness, and fault classification for tapeout sign-off.
✓ Architect a complete DFT solution from RTL to ATE, including low-power DFT, ISO 26262, and fault diagnosis flows.
Requirements
● Solid RTL design knowledge and digital logic fundamentals. Basic familiarity with synthesis flow and setup/hold timing.
Description
This course delivers the complete engineering foundation for modern ASIC Design for Test, taught at the depth and precision required by industry professionals.
You will master every layer of the DFT stack - from the mathematical principles of fault models and ATPG, through scan chain architecture and multi-clock domain management, to IEEE 1149.1 JTAG, test data compression, on-chip clocking for at-speed test, low power DFT, and memory BIST.
Every topic is grounded in real tool flows using Siemens Tessent and Synopsys TetraMAX, with direct reference to the exact reports, constraints, and sign-off metrics you encounter in production ASIC projects.
This is not a survey course. It is a structured, engineering-grade curriculum designed for ASIC engineers who need to architect, implement, and sign off DFT on complex SoC designs.
What you will be able to do after this course
- Design and sign off full-chip scan architectures with balanced chains and lock-up latches
- Generate and interpret ATPG patterns with >99% Test Coverage
- Implement IEEE 1149.1 JTAG and IEEE 1500 embedded core test
- Configure test data compression to reduce ATE test time and cost
- Architect on-chip clocking for TDF and path delay at-speed testing
- Meet automotive ISO 26262 ASIL-D coverage Requirements
- Write STIL protocol files and manage DFT deliverables to tapeout
Who this course is for
■ ASIC/hardware engineers with RTL background moving into DFT, and verification or physical design engineers needing DFT expertise.
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